`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/09/26 15:27:04
// Design Name: 
// Module Name: asyn_fifo_wr
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module asyn_fifo_wr( 
    input   wire            clk             ,
    input   wire            rst             ,
    input   wire            full            ,
    input   wire            wr_en           ,   
    output  reg    [5:0]    wr_ptr          ,   //地址指针
    output  reg    [5:0]    wr_ptr_gray         //地址指针gray码
    );
    
    wire    [5:0]   wr_ptr_nx;
        
    assign wr_ptr_nx = wr_ptr + (wr_en & (~full));
    
    always @(posedge clk or posedge rst)
        if(rst)
           wr_ptr <= 6'd0;
        else 
           wr_ptr <= wr_ptr_nx; 
    
    always @(posedge clk or posedge rst)
        if(rst)
           wr_ptr_gray <= 6'd0;
        else 
           wr_ptr_gray <= (wr_ptr_nx>>1) ^ wr_ptr_nx;     
    
    
endmodule
